What’s All This jFET Matching Stuff, Anyhow ?!

JC Maillet, posted Oct22/2020 …

jFET transistors are considered “DC matched” when their respective Vgs(off) and Idss values are identical, or close enough, to each other.

Of course, there is more to jFET device matching not covered by those two parameters – for example, the output resistance ‘ro‘ in the Pinch-off region. But, as far as basic characteristic equations are concerned, Vgs(off) and Idss pin down the transfer curves that defines device large-signal behavior when operating within a circuit.

If we were to sit down and try to estimate these values through testing we find that even over a lot of two or three hundred devices it is nearly impossible to find even one matched pair, let a alone a single quad, that might land bang-on for both variables …


BACKGROUND: THE MOOG BIPOLAR TRANSISTOR MATCHING TECHNIQUE

Robert “Bob” MOOG published a useful test for matching bipolar transistors … the reason why this works with bipolar devices is because their characteristic equations are set by one process variable only, namely the saturation current ‘Is‘. In the jFET’s, the two parameters Vgs(off) and Idss offer two dimensions of independent and random variability.


MOOG’S TECHNIQUE APPLIED TO JFETs ??!

If we apply Bob’s idea to jFETs we might come u with something that looks as follows …

the circuit is listed by its author as “An Improved jFET Matcher”, where the idea is to force a controlled 450uA DC current through the device while monitoring its Vgs (bias point) voltage …

However, … in this scheme it is easy to show that by shifting Vgs(off) and Idss in the opposite direction, and by the right amount (something that could randomly occur in the real), we could easily obtain false-positive matches rather than true ones. In fact, the likelihood is in favor of the false-positive match due to the continuous and not-so-limited nature of the false-match subset created thusly.

We can alter these numbers and run circuit simulations to confirm the principle. For example, by dropping Vgs(off) by a substantial 100mVolts and increasing Idss through an increase in Beta (lambda remaining the same) we can arrive at a false-positive test voltage 1mVolt off from that of the reference device …

To achieve this, we vary Beta on the second device until their current profiles cross at the 450uA line … nearly the same operating point as far as the devices see it

This way, we could go on all day coming up with similar false-positive combinations … a few questions pop up then – like, what is the likelihood of getting a false-positive over a true positive … ??! or, what is a “realistic” Vgs(off) spread within the locus of false-positive combinations … ??! (from my personally extracted 2n5457 data I’m guessing 100mV max most likely … but only physical testing over large lots can answer that questions)


COMMENTS & CONCLUSION

Even if you do your diligent testing, you’ll still never get jFET’s to match “bang on” unless you get into thousand-fold sample sets, or loosen your matching criteria significantly …

Better time spent trying to figure out how to design jFET circuits that can operate “optimally” without the requirement of tight device matching … or better yet, any kind of matching at all …

“Paradigm Shifter” jcm(c)2017



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