PARADIGM SHIFTER // JC Maillet (c) 2017
[AI generated, please fact check …]
JC Maillet Paradigm Shifter
The “Paradigm Shifter” is an electronic circuit design concept developed by JC Maillet, focusing on a novel approach to building jFET-based phasers It challenges the traditional assumption that tightly matched jFET transistor sets are necessary for effective phasing Instead, the design utilizes randomly un-matched jFETs, applying proportionately scaled control voltages to each device’s gate individually This method aims to achieve superior phasing performance by ensuring each device is modulated by a near-identical proportional Vgs span, synchronized in time, rather than relying on a single control voltage for all devices The design argues that the all-pass phasing circuits are indifferent to whether the voltage-controlled resistance (VCR) elements are matched or not, as long as the AC resistance time functions are closely matched This approach is presented as a more economical and practical alternative to the extensive device selection required to find tightly matched jFETs, which can be costly and time-consuming The design is intended to provide greater versatility, including manual Depth and Offset controls, and is presented as a way to build a potentially better-sounding jFET phasor
Another original design concept …
PREFACE
In building jFET-based Phase Shifters the universal assumption is to make use of well-matched jFET transistor sets – devices that are meant to operate as voltage-controlled variable resistance (VCR) elements. This assumption is paired with a second one; namely, that a single Control Cv Voltage be applied to all gates in unison.
These two assumptions go hand in hand in forming the strategy that was used by Keith Barr at MXR in mass manufacturing the early P45 and P90 Phasors. Everybody seems “inclined” to copy his approach even through the man had a strong advantage most hobbyists don’t … ie., the ability to estimate Vgs(off) using a 15nA test current while sourcing pre-matched devices directly from the manufacturing plant. (see data sheets for measurement details)
But this pair of constraints in fact has really much more to do with the economy of the original manufacturing process employed in the past at MXR than it does in implementing a broader theory of jFET BASED PHASE SHIFTER DESIGN in general. And, we could wonder, how does MXR/Dunlop perform their matching nowadays ?! And, is the matching as tight as it once was ?! An interesting question, though one that becomes completely irrelevant in light of the present PARADIGM SHIFTER re-design …
In this regard, check out my other jFET PHASER related material …
Phase-90 Cv ANALYSIS/Simulation
What’s all this jFET Matching Stuff Anyhow
But, from a purely electronic point of view this peceived design requirement is completely irrelevant – it’s mainly a manufacturing strategy. It’s also one that helped Keith Barr produce a very compact commercial product that worked consistently well. Otherwise, there’s no real need for such constraints when the goal is to build a more complete (and optimized) jFET phasor design. In fact, lifting that condition can actually be helpful in the quest for a better phasor response.
The assumption typically made is that we can get matched devices from somewhere, and then get on with building the jFET phasor of our dreams. In reality all this needs to be questioned, especially when we consider what kind of testing/matching methods are being passed around online.
Like, does anybody ever double check the specs on their lot of matched jFET devices ??! Or, has anybody ever measure the specs on the devices used in vintage MXR units ??!
Somehow, you never see this mentioned anywhere …
I’ve spent some time looking at the probability of getting a tightly matched pair or quad based on a lot of properly characterized jFET devices and I will say it’s basically impossible to get a very tight pair or quad (+/- 10mV) without selecting through about 50 or 100 devices at least. And that doesn’t mean that this tight-knit group will necessarily land in the right range of voltages. That’s where tapping into the flow of device production comes into play.
If we consider that MOUSER is now selling 2n5457’s at $2.10 a piece (or $148us/100) things can get rather pricey quickly for someone seeking to “achieve” a tightly macthed quad …
So, is there an alternative ?!
Well, yeah – of course there is … why nobody has mentioned it before is beyond me // well, sorta …
The first thing to understand is that the individual devices don’t care how the circuit that modulates their gate actually does its job – whether, it’s being done in tandem or individually (see Interfet AN105). The devices will never “know” and don’t care either way.
Indeed, some online forums offer erroneous jFET test jigs. If you’re using such a set of devices and they e nd up producing a phasor that happens to work very well, consider yourself lucky! My analysis of the situation tells me that some of these test jigs can produce errors well into the 100mV range, which on a circuit that produces an LFO amplitude of 300mVpp is quite considerable.
From this observation we see that we can probably get way better phasing from a pair or quad of totally un-matched devices running on individually adapted Cv voltages than from a pair or quad of devices that were spec’d in a questionable manner and running on a single Cv voltage. This also explains well why Keith Barr needed spec’d jFET devices to get good consistent performance from pedal to pedal.
Again, Keith Barr of MXR fame was able to produce the Phase 45, 90 and 100 only because one of his school buddies was working for a major semiconductor company at the time and they were able to arrange for someone to select spec’d devices off the production line (using a 15nA threshold test platform).
The side-chain architecture of all three MXR phasors relies directly on the use of a single control voltage driving a set of matched jFET’s devices … obviously this is done to save space, offering nothing but a SPEED control, etc. and providing modestly good phasing performance … to be fair, many players liked the MXR stuff because it didn’t produce extreme phasing like the EHX OTA-based (ie., David Cockerell’s) stuff does. But, that’s just comparing the preference in effect quality of one style of phasor architecture against another here. My main interest here lies in exploring the possibility of building a possibly better sounding jFET phasor – using the same or slightly improved signal path – while at the same time provide a full versatility side-chain; ie., with DEPTH and OFFSET (manual) controls.
Indeed, the purpose of the work done here is to show that very-well controlled Phasing effects can be achieved more economically (ie., with much less device selection effort) by using random/un-matched jFET devices. You could even use devices of different designation as long as they are n-channel jFET’s
My experience suggests that it is much easier to achieve optimum phasing performance following this approach than, say, by using loosely matched devices in a single-CV environment.
For one, this saves time and cost as much fewer jFET’s need to be purchased. In contrast, perhaps fifty to a hundred would be required to produce just one quad of tightly matched devices . Not to mention that you’ll have a much better “overall” idea of what your circuit is doing.
To get an idea of the low-level probability of obtaining even a single matched quad within a lot of few hundred devices (using +/-5mv error on Vgs(off) as a yardstick) see my collated 2n5457 data –>> here)
My PARADIGN SHIFTER design challenges this ubiquitous “matched device” assumption, by instead making use of randomly un-matched devices and applying proportionately scaled CV’s to each device gate individually.
The reason why this even works is because the all-pass (phasing) circuits that perform the shifting don’t care exactly how the time-varying resistance takes place or is created // coming either from matched or un-matched devices, that is – it simply doesn’t matter. In fact, we could in principle use a mix of jFET’s and optical elements to build a phasing circuit … albeit impractical in nature, it would still produce a working phasor circuit. In other words, the type(s) of VCR elements used doesn’t matter as far as making things work – headroom being an entirely different matter altogether however (that’s a secondary thing here).
In the end what is really required for obtaining good Phasing performance is a close matching of all (AC) resistance time functions produced by the jFET VCR’s. My approach makes sure each devices is modulated by a near-identical proportional Vgs span, performed synchronously in time.
THE FIRST REQUIREMENT: A MATCHED CONTROL RANGE
When employing jFET devices in the capacity of phasor circuit Voltage-Controlled Resistances (VCR’s) the idea is to make use of all or just a portion of the total control range. This reasoning is clearly justified by the Interfet application note linked to above.
BUILDING THE “PARADIGM SHIFTER”
HOW TO BUILD THE ULTIMATE 4-stage SHIFTER USING UN-MATCHED jFET’s
STEP 1
you will have to acquire at the very least four (n-channel) jFET transistors and for this project I recommend getting four 2n5457 jFET’s, although other jFET’s can be used as well with slight change to the methodology. Genuine 2n5457 devices are still somewhat common and can be obtained from smallbear electronics:
http://smallbear-electronics.mybigcommerce.com/transistor-fet-2n5457/
the datasheet for this device can be found here. You will notice that the range of turn-off voltages “Vgs(off)” is listed as spanning -0.5v to -6.0v in the datasheet, though in practice I’ve found the majority of 2n5457’s that I tested had Vgs(off) values measuring between -2.2v and -0.8v
for the purpose of this project I find it’s easier to work with devices whose Vgs(off) value lies below 2 volt in absolute terms … this, however, is not mandatory by any means – it just helps make things easier here. If instead, you wanted to try other jFET’s that you may already have on hand, even those with smaller Vgs(off) voltage ranges such as the 2n5484 or J201 these should be fine as well. All we might need to do is alter the LFO section to accommodate the highest jFET voltage device; again the rest of the Cv’s can be scaled via trimpots.
NOTE: Vp, which equals -Vgs(off), is referred to as the pinch-off voltage. For n-channel devices Vp is positive valued and Vgs(off) negative. In characterizing our devices we may speak in terms of either variable.
The first step is to grab four jFET’s and measure (or rather, approximate) their Vgs(off) voltage as closely as possible … one quick and easy way to get a good enough approximation to this value is by simply using a DMM and a fresh 9volt battery – as shown below … the internal resistance of the DMM will produce an extremely low current in the Device Under Test (D.U.T.) thus accurately approximating the true Vgs(off) voltage value for that device …
Lo and behold, the first four 2n5457 devices that I picked out of the bag fell above the Vp=2v mark … the actual measured approximations to the real Vgs(off) values are then given as: Vp1 = 1.996v, Vp2 = 1.368v, Vp3 = 1.534, and Vp4 = 1.806v
STEP 2
Calculating Scaling RATIOS …
next, we want to single out the one jFET device whose Vp voltage is largest in magnitude, or the most positive (note: Vp voltages are negative for n-channel devices) … we will refer to this “largest” voltage as Vp1 … this way, all other Vp voltages will be less in absolute magnitude
we can write this condition as Vp1 > Vp2, Vp1 > Vp3, Vp1 > Vp4
at this point we can form ratios between Vp voltages to the first voltage and refer to them as scaling factors:
a2 = Vp2/Vp1, a3 = Vp3/Vp1, a4 = Vp4/Vp1
notice that the minus signs will cancel each other out in the ratios, so we can simply divide the voltages in their absolute terms to get the ratios
thus, we get the following scaling factors
a2 = 0.868, a3 = 0.770, a4 = 0.906
note: the actual ordering of devices in the circuit is un-important; as mentioned above, the circuit just doesn’t care who’s who here … all that matters is how channel resistances track with each other in terms of normalized CV drive (… again, refer to the Vischay paper above for a justification of the normalization process)
STEP 3
Measuring Trimpot Values …
we will be using 1Meg trimpots to establish Control Voltage (CV) scaling that are commensurate with the aforementioned ratios … to do this we first need to measure the full value of the trimpots (end-to-end), as they can deviate considerably from their listed value … ie., assuming they measure 1Meg exactly would be a mistake that would certainly invalidate the whole approach … in other words, this is something that needs to be done with a sufficient degree of accuracy and attention …
STEP 4
pre-Setting the Trimpots …
next, we take the ratios defined above and multiply them to the real (measured) trimpot values as to know exactly where to set each corresponding trimpot prior to installation in the circuit … this needs to be done beforehand because once they are in the circuit all the trimpots will be paralleled and the scaling adjustment can no longer be done correctly the same way …
once the trimpots have been adjusted to their “set” value they need to be kept in that position during the PCB population phase of the build, so a little care needs to be observed once the trimpots are set to their calculated ratio … the choice to associate which trimpot with which jFET device is completely arbitrary at the onset of course
but once the choice is made and trimpots are adjusted, from then on each set trimpot needs to remain associated with its corresponding device … that much should be obvious to the reader
STEP 5
Making the board …
the PCB card that I used for my working prototype was CNC’ed using single layer artwork done in expressPCB:
it was then converted to Gerber format using the pdf2gerb PERL utility:
http://swannman.github.io/pdf2gerb/
If you would like to etch your own board I offer a PDF of the artwork (2.028″ x 3.760″)
PARADIGM-SHIFTER-PCB2.028×3.760jcm(c)2017
the pcb is designed to float down from the top box cover using 1/2″metal (standoff) studs … these can be obtained at smallbear:
http://smallbear-electronics.mybigcommerce.com/threaded-stud-4-40-x-1-2-high-x-187-o-d/
http://smallbear-electronics.mybigcommerce.com/screws-flat-head-4-40-x-1-4-bag-of-5/
STEP 6
Circuit Assembly …
the board is quite straightforward in design … the first thing that stompbox builders will notice is the complete absence of signal caps at the input and output // this is no accident, it is done to provide maximum signal fidelity … if you feel the need to have them included please be my guest, in general they are not needed
the circuit is powered by a bi-polar +/- 7.5v power supply (PSU) circuit that is fed by a common 9vac power adapter … that’s VAC and not VDC
note: 9vac adapters can often be found at local thrift stores for a dollar or two … you might need to change the plug end, that’s all
http://smallbear-electronics.mybigcommerce.com/2-1-mm-right-angle/
among other things, this bipolar power circuit allows the signal-path circuitry to run in DC-coupled mode at both ends – assuming there are no external DC sources present (which is typically the case anyway) … in so doing, this greatly simplifies the design of the signal path, besides offering a high-fidelity solution … for those who prefer single-battery operation a little bit of circuit massaging would be required to adapt (… a simple and straightforward exercise)
PARADIGM-SHIFTER SCHEMATIC
PARADIGM-SHIFTER LAYOUT AND WIRING
notice the absence of a scaling trimpot associated with the Vp1 device … in that case the MASTER CV line is jumpered straight to the gate of the Vp1 device (the one denoted by the * symbol in the layout drawing) and the 50k trimpot preceding the 5k Master CV pot is set so that the total max voltage excursion seen there equals Vp1 in volts
As stated above, the in-circuit order of all jFET’s matters not – the only thing that matters here is the association between scaling trimpots and the (other) remaining devices other than the Vp1 device
Also, notice the range limiting resistors set across the jFET’s are listed as 10M // something that you will never have seen before in a jFET Phasor circuit … in comparison, the MXR Phase45 and Phase90 have limiting resistor values of 20k (10k + 10k) and 22k which are much lower. This provides a safeguard against driving devices past their Vp point and causing a loud “knock” at the output … typical values seen in optical phasor circuits might be more like 100k … 10M is as close to infinity as anything practical, and shows that the jFET channel resistance values play a completely dominant role in setting the overall Phasing performance // if the principle I’m offering here turned out to be bogus by nature it would surely show itself here, This observation provides proof of concept and confirmation of resistance range matching … It also provides a full phasing operating span, something the MXR units do no provide!
Again, to be clear, this allows the devices to exercise a much wider range of variation than anything seen before in jFET phasors … of course, how much of that range is to be used will depend afterwards on the taste and needs of the player (a secondary consideration for me in this exercise) … the main point here is to provide us with the ability to explore the full range (or any part herein via the OFFSET control) of resistance variation. More importantly the same proportionality of AC resistance variation (in normalized terms) can be obtain by all jFET device irregardless of their specs!
Steve Daniels at Smallbear Electronics has kindly put together a “parts” kit for this project:
STEP 7
Calibration and adjustments …
once the outboard controls and power jack have been connected we are ready to do some electrical testing on the circuit
if you notice, a 3.9v Zener diode is used to provide back voltage to supply the floating ground reference on the oscillator circuit …
turns out I was only getting around 2.50v across the Zener when biased with a 2k2 resistor … likewise, I only got 2.0v from a 3v Zener – so I’m assuming this is a characteristic of these low-voltage Zeners … normally, with a 8.2v Zener I can get pretty close to rated voltage using only 1mA or 2mA of bias current … the datasheet shows rated voltages achieved at 64mA which would be a waste of current in this circuit … the important point is that 2.5v provides more than enough voltage when dealing with devices whose Vp value falls below 2v … slightly higher voltage Zeners could be used if 3.9v ones aren’t available
as well, if other types of jFET’s are used then one would need to provide a Zener voltage that exceeds it by some amount, to have sufficient range in the OFFSET control … in other words, use whatever Zener diode that fits your purpose – you might have to change the biasing resistor that’s all
case in point, to estimate the current biasing the Zener we simply divide the voltage difference between source and Vz divided by the bias resistor value …
in my case:
(7.5v – 2.5v ) / 2.2k = 5v / 2.2k … which is a little over 2mA … plenty good
the 50k trimpot that precedes the OFFSET control needs to be set to Vp1, or a little further if you feel like experimenting … at first I recommend setting it so that the floating ground line in the oscillator lies near Vp1 as closely as possible
next we need to set the value of the LFO range limiter trimpot // probably the trickiest part of the whole build …
this is the 50k trimpot lying between the LFO output and the 5k DEPTH control … by setting the LFO RATE at a super low speed (almost static), with the OFFSET control as closely to half-point as possible, and also with the DEPTH control set fully open, we set the range limiting trimpot to a value so that the maximum voltage at the DEPTH control reaches 0v (or just under) as closely as possible … a scope will make this calibration part much easier to accomplish, but a DMM should be able to do the job provided the LFO is running slowly enough … only patience and time is required to get this part right
btw, at this point you may notice that the minimum voltage swing now reaches below Vp1; this is fine as you’ll see in the end …
Now, let’s go back and return the DEPTH control back to zero/off position and sweep the OFFSET control while measuring the oscillator’s floating ground voltage … you should be able to see a Vp1 to 0v sweep in manual mode … nothing there should change from before adjusting the range-limit trimpot
The goal in the end is to be able to place the triangle-like CV waveform anywhere inside the 0 to Vp1 range …
in case you’re wondering, the 50k “range” trimpot should limit any current flowing into the device gates if the control voltage where ever to exceed 0v by much … still, care should be exercised here … specifically, there is nothing useful to be gained from exceeding this (upper) 0v limit anyway as the more useful area of operation lies near Vp1 anyway – the same goes for all devices with respect to their individual Vpi limits …
the whole point of this exercise is to allow exploring any arbitrary part of the full control range, including the full range itself … to see what sounds most useful -either the whole range, or only one part of it … our ears will guide us at that point
… because the other gates have their control voltages set by the CV voltage thru their associated scaling trimpot, each gate will automatically receive the same normalized proportion of the main control voltage … in other words, when CV reaches Vp1, each gate will see their corresponding Vpi voltage; when CV is zero, each of the other gates will see zero as well; and any percentage will be the same throughout … for an understanding of this normalized relationship take a careful look at the Vischay paper referenced above
with the circuit connected to a guitar and amplifier the OFFSET control alone should produce discernible amounts of “manual” phasing … if this doesn’t take place then a mistake was made and steps need to be retraced carefully … you can now set the OFFSET control somewhat within the middle of the manual PHASING range and try increasing the DEPTH control a little bit at a time until things get choppy // alternating between these two controls should lead to an optimal setting when seeking even performance …
in my build I found that the DEPTH control only needs to be set about 1/4 way up to get a full and even phasing effect … notice that the circuit can provide way more than what might be considered useful to most players, likely going into heavily chopped territory with the DEPTH control fully cranked …
STEP 8
Final construction and playing …
I designed the PCB so that it would fit in a Hammond 1590BB size box with enough room left for 16mm panel mounted pots and SPDT toggle switches placed on one side-wall, and 1/4″ jacks on the other … with a little breathing room to spare for the footswitch and top-mounted SPEED control
this way the circuit board can also be lifted easily without removing everything else; just in case a part needs to be changed or something …
once the whole works is finished the option of doing final testing using a signal generator and scope can be exercised … I recommend using a 300hz sine-wave with about 100mV pk-pk signal amplitude to verify absence of waveform distortion and other aberrations … the functionality of the OFFSET and DEPTH controls can easily be verified this way too using a dual-trace scope
playing the unit involves understanding where the controls need to be set for best/desired effect … again the key lies in placing the OFFSET control in the right place, and from there setting the DEPTH control appropriately … by doing this, we can operate all jFET’s exactly to our choosing in the same proportion and center-point within their normalized VCR range … to my knowledge no other jFET phasor provides this control over the span of resistance variation // an idea that is based on my original Univibe LFO mods and used in my other phasor designs as well.
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CONCLUSION
the circuit described on this page gives a degree of modulation I haven’t experienced in other two and four stage jFET phasors … moral of the story, driving “loosely” matched jFETs with a single Vc doesn’t yield good final results as when using an approach that custom adjusts (through correct measurement) the driving Vc to each jFET taken randomly from a batch of un-matched devices … dispelling the idea of a need for “jFET matching” in the first place …
have a nice day, eh
holy sheet JC, that is one bad-ass lookin’ ride.
hopefully one day i can work up a perf or vero and try my hand at one.
my experiences matching jfets have been pretty dismal. so far the prevailing truth seems to be if all else fails, try some j201’s.
any chance you may have a spare board you’d be into selling?
would love to populate it so i could rock a stupid youtube video.
love phasers. this looks really cool, and i believe i’ve got everything kickin around my dungeon.
peace, happy new years, and rock on bud!
thanks!