jFET Transistors : Getting to know Vgs(off) and Idss

JC Maillet, posted Oct22/2020 …

A quick look at any good circuit theory book and you generally find jFET device equations written in terms of the process-dependent constants Vgs(off) and Idss.

Together,Vgs(off) and Idss pin down the CHARACTERISTIC relationships which in turn define the jFET’s large and small scale behavior..

The purpose is to show where these two parameters lie within the device’s transfer curve sets. Then, we can make some observations about the techniques and accuracy of the measurements used for extracting their values.


All results presented are generated from computer based circuit simulation software using “mean-value” models for the 2n5457 n-channel jFET transistor. This modelling is provided by Texas Instruments as part of their freeware program “TINA-TI” version9.


Vgs(off) is defined inside the Id(Vgs) set of transfer curves, where Vds is stepped in discrete/fixed values and Vgs is continuous. Because these curves lie close to each other in a parametric sweep it is often customary to represent these curves by a single one, especially when writing things down on paper by hand. This can be a source of confusion if overlooked.

Below is displayed the simulated results with Vds values swept between 2volts and 10volts, in 2volt increments. All curves transition to a zero value precisely at the Vgs(off) mark, which is what defines this important voltage limit.


Idss is defined inside the Id(Vds) set of transfer curves, where Vgs is stepped in discrete/fixed values and Vds is continuous. Here, Vgs is stepped in two values, 0v and Vgs(off) – with the first being referred to as the diode (dual electrode) or “current-source” curve, and the second representing the onset of complete cut-off (ie., Id=0 regardless of Vds). Idss is defined as the current flowing through the devices when Vgs=0v and Vds=-Vgs(off), the later often referred to as the Pinch-Off voltage (Vp), which in turn is used to define the device’s Pinch-Off region.

About the Pinch-off region … and ‘ro’

In this region the modeling is comprised strictly of linear equations (ie., straight lines). This is where the modeling parameter ‘Lambda’ (the inverse of the “Early” voltage) comes into play. In fact, Lambda is directly tied to the slope value of individual lines inside the Pinch-off region.

For a real jFET device this area of the modeling would have a degree of curvature to it (see ON-Semi datasheet figure 2) and so some modeling deviation/error is to be expected here. In theory, as long as our testing is done at a sufficiently low voltage relative to the total available device operating range – in this case, 9volts against 25volts total – we can accept this linear modeling as being somewhat good.

To be fair, trying to estimate the exact degree of modeling error in this area is next to impossible. It is for this very reason that we should never expect very accurate estimates for ‘ro’; the so-called incremental output resistance of the device which plays an important parameter later in performing small signal analysis.

The ‘Early’ voltage (Va) provides a good low-computation substitute for ‘ro’ – namely, thru the following approximation …

ro ~ Va / Id

where the Early voltage is used in inverted form as …

Lambda = 1 / Va

from which we then get …

ro = 1 / (Lambda x Id)

suggesting that ro varies inversely to bias current


Depending on the level of accuracy we are looking for, we have several options for obtaining values.


We can use a 9volt battery and a digital multi-meter (DMM) to get a rough idea of a device’s Vgs(off) voltage. The idea is to have the meter’s internal (high values) resistance act as a biasing resistor for the device under test (DUT); which is done as follows …

In this diagram two circuits are simulated, the top one using a 1Meg ohm resistor to model an economy DMM’s internal resistance while in the second using a 40Meg ohm resistor to model the internal resistance of an higher-quality DMM. The difference in measured/simulated values is around 30mVolt – not an insignificant number in some designs.

Still, further sims (your turn!) can be done to show that the variation in test voltage produces a very small measurement error here; so in not-overly-strict situations we can obtain relatively useful “ballpark” Vgs(off) data using this approach

… with an immediate and easy fix if high accuracy is needed, a degree of error which can always be estimated using basic error/measurement analysis


Again, we can use a 9volt battery and digital multi-meter (DMM) to get a rough idea of a device’s Idss value. By definition, Idss is the current flowing through the device when it is diode (ie., di-electrode) connected, and fed by a supply voltage corresponding to -Vgs(off). Unless we need to measure this current value with very high accurately most people simply apply 9volts directly in the test; assuming -Vgs(off) is below 9volts that is …

Sometimes, depending on the value of Vgs(off) being measured, the results will be within the error resolution of the DMM anyway (especially in the 2-significant-digit scales); in these cases having a more complicated test jig brings no benefit.

Here’s another view, in context of the diode curve, showing this linearly simulated 35uA error between the two measurement points ….


  • An accurate method for extracting Vgs(off) involves using a high-accuracy volt meter exhibiting very high internal resistance in conjunction with a relatively unrestricted test voltage source. An accurate method for extracting Idss involves using a high-accuracy ammeter with a test voltage source set very closely to -Vgs(off).
  • A 9volt battery and economy DMM (defined as having an internal resistance of 1Meg ohm) can be used to get a ballpark value of Vgs(off). If we use the 1Meg-vs-40Meg comparison results above we can see that we could almost distort the reading by an extra 30mV and probably be pretty close to the real value. For an accurate Vgs(off) value the best thing is to use something with at least 40Meg ohm of internal resistance.
  • The Idss test doesn’t involve the same kind of interfacing issues as the Vgs(off) test does, but the difference between doing the test at -Vgs(off) and 9volts (say) should be carefully considered before-hand. In cases where the test voltage is not lying in an area of considerable inflection we can rely on having small degree’s of error, which will generally play a negligible role in most practical applications. Hence, the general acceptability of doing a real-world test at 9volts for the 2n5457 n-channel jFET’s.
  • The testing methodology presented here contains no form of negative feedback – either in devices, components, or processing. As well, it avoids the use of any intermediary devices that could introduce “unseen” offsets that would then lead to further measurement error. The direct approach presented here relies only on DMM accuracy and DMM probe specs.

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