jFET DOUBLER (redux) // jcm(c)2020

JC Maillet, posted Oct22/2020 …


A recent review of “up-Octaver” designs prompted me to apply large-signal analysis techniques to the general class of FW Rectifiers … by using TINA-TIv9 as SPICE engine, both DC-Transfer analysis and (real-time) TRANSIENT analysis can be used to describe and measure a DEAD-BAND that occurs generally in the transfer of signal through a FW rectifier stage …


This is particularly relevant in the context of “up-Octaver” circuit dynamics, as it serves to explain why some circuits feel more or less “gated” than others.


By comparing a few of the better-known (successful) vintage designs we see that a common structure is generally employed in creating the up-Octaving FW Rectifier circuits: (i) a “pre-gain” amplifier to boost the input signal, typically made variable, (ii) a phase splitter/inverter to provide anti-phase drive signals and (iii) a rectifier/doubler stage – sometimes the last two are combined in one …


Since the Phase Splitter/Inverter part typically operates at unity gain (except for transformer based designs), we can omit it from the picture which leaves us to consider the role of the two remaining design variables, pre-gain and rectifier threshold (aka “the dead-bad”)

From this we can then analyze known “up-Octaver” designs in terms of a basic structural trade-off: pre-Gain versus Dead-Band/Threshold … a “ratio” that eventually translates to the player as “dynamic gating” …

looking at things from these specs alone …

  • Roger Mayer “Octavio” … 38db max pre-gain (unloaded) … 300mVpp “Ge”
  • Shin-Ei “Super Fuzz” … 20db max pre-gain … 50mVpp deadband
  • Dan Armstrong “Green Ringer” … 9.5db pre-gain … 600mVpp “Si dead-band”
  • Roger Mayer “Octavia” … 15db max pre-gain … 600mVpp “Si dead-band”
  • The stock “Green Ringer” is the most gated of the four, while the other three relatively less.

    The “Super Fuzz”, though not strictly an “up-Octaver-only” type of circuit, has a FW Rectifier section that hardly gates at all – making the overall circuit a very smooth behaving Octa-Fuzz …


    The jFET DOUBLER ™ RG Keen (c)2002/2009 schematic consists of a jFET based (unity gain) Phase Splitter/Inverter, a jFET based FW-Rectifier and a dual-jFET high gain Mu-stage – in that order (!)

    using five n-channel jFET devices in all …

    If we focus on the rectifier stage for a moment, simulations show jFET circuit dead-bands ranging from 560mVpp (for center-value 2n5457’s) to 240mVpp for (center-value J201’s).

    These are quite size-able …

    As the rectifier gain curve below shows, in the absence of any pre-gain a nominal guitar signal (eg., 200mVpp sine-wave) would be stuck inside the dead-band range where output gain is low, resulting in poor S/N overall. Following this then with a high-gain (un-buffered Mu-stage) amplifier and we have a good recipe for producing lots of noise, … and with little to no “up-Octaving”

    SPICE simulation suggests the jFET DOUBLER ™, as it was originally presented, could only produce a strong “up-Octave” once input signals started approaching 1Volt peak-to-peak in strength; that is, for a FW section implemented with center-value 2n5457 devices … -> with Vgs(off) lying close to -1.37volt

    According both DC and AC transfer curves a nominal guitar signal (200mVpp) would need a pre-gain factor of at least x4 or x5 to begin achieving good Signal-to-Noise (S/N)

    Also, note there is a typo in item 3. of the “directions” … where it says to “match R3 to R2”, that should read “match R3 to R4” … otherwise matching R2 to R3 (2k2) will kill signal at the input, where a high-Z passive LP filter is set up (… not so good for S/N either).

    Btw, using an un-buffered “Mu-stage” at the output of a circuit is begging for trouble as the gain of the circuit can easily be squashed by a low impedance load. For example, un-buffered “Mu stages” tend to die when placed in front of low-Zin “Fuzz Face” type circuits


    Another thing I noticed that is very important here, has to do with correcting for rectifier device mismatch.

    It turns out that the overall jFET based FW Rectifier circuit is not that sensitive to Vgs(off) mismatch – which is a very good thing. On the other hand, the BALANCING trimpot only acts on one side of the FW Rectifier. In fact, all it does is scale down signal on that one side – compare this to the Shin-Ei BALANCING circuit, which affects device bias and gain at the same time.

    The point here is that if the stronger jFET is placed on the wrong side the BALANCING trimpot will only act to further imbalance the circuit – something that might not have occurred to many as they assumed they were working with “matched” devices. So to make things easier for everybody there should be two sets of training wheels on this circuit.


    Some may find themselves bemused by my use of “FW Rectifier” when discussing circuits that obviously don’t work exactly like rectifiers, strictly speaking. And this has to do with the bottom capacitor in circuits like the jFET DOUBLER and Shin-Ei “Super Fuzz”.

    To be clear, the capacitor does two things: (i) it increases the AC gain (output) of the waveform during the part of the cycle where either transistor is working, and (ii) it stabilizes the common node voltage (at the Sources) and averages or slows down the fluctuation of voltage at that common node, resulting in a rounding of the tip that is normally seen in a more “ideal rectifier circuit.


    One way to fix all this is by simply moving the Mu-stage to the front, and we basically keep everything that’s there already. Of course, the pre-gain amplifier could be designed and built some other way – but there is something pleasing about simply shuffling things around. After all, it does serve as a good jFET demonstration circuit.

    Shown here is my complete re-adaptation, with variable input gain and a variable HI-CUT function in the Mu-stage.


  • the “Mu stage”now operates (correctly) with negligible down-stream loading.
  • the Mu-stage is configured to provide a boost factor of x10 with the DRIVE control set to MINIMUM.
  • A gain factor of 10 is necessary to bring a 200mVpp signal up to 2Vpp, which will drive the FW rectifier into a strong up-Octave waveform. Higher pre-gain DRIVE levels can be obtained in the Mu-stage by reducing the 5k DRIVE POT value (to 1k) and/or increasing the HI-CUT pot to 100k (and halving the HI-CUT cap to 47nF) … warning: doing both produces really high levels of signal gain

    Alternately, => Some DIY’ers may find incentive in choosing rectifier devices with very low Vgs(off) values (especially, low Vgs(off) J201’s, for example) … the lower the better if one wants to explore the higher gain/sensitivity potential of the circuit

    Compare this to my recent “Green Ringer” mods


    The 1k resistance at the output of the rectifier stage is quite good (low enough) in itself as far as output “drive” impedance goes. If someone felt they needed even more output drive an op-amp based “trans-impedance” stage could be introduced to provide “buffered” drive on the output … but like I said, 1k is still very good. And notice as well, the output pot could be wired as a variable “loading” resistor (with output taken at the top and the sweeper grounded) instead …

    Since the voltage swing is at least double at minimum DRIVE settings (and max VOLUME) and goes up from there with increased DRIVE, there is no need to follow the rectifier stage by any kind of amplifier stage – unless for the specific purpose of creating distortion. But, this can be accomplished with diodes as well, just as in the Shin-Ei “Super Fuzz”.

    As a stand-alone up-Octaver alone, this circuit doesn’t really need buffering – in principle, it should be able to drive a Fuzz Face to some degree (… needs verifying).

    By simply by moving the Mu-stage to the front and cleaning things up a bit all the required elements for a strong, yet low’ish-noise, guitar oriented design should happen …

    Of course, the standard Mu-stage biasing requirements apply here and the use of 10k resistors in the cathodyne phase-inverter/splitter strongly reduces the likelihood of Idss being exceeded when employing 2n5457 devices …


    I took the opportunity to simulate my revision of the jFET DOUBLER circuit using false-positive device specs (with Vgs(off) off by 100mV). I’m guessing this what DIY’ers could be using in extreme cases, and found that the training wheel idea worked well at re-centering the response. We just have to include them on both sides to preclude having to swap devices later ….

    This shows how well the BALANCING scheme works when the correct trim-pot is used … One more simulation shows the circuit in action with high-gain components …


    I have not built or physically tested this “jFET DOUBLER (redux)” nor the “Green Ringer (redux)” but I have high confidence that the circuit simulator wasn’t lying to me over the last few weeks …

    so, I leave it up to you

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