jFET Characterization Technique using only 9v Battery and DMM
As mentioned in my other post about accurately characterizing a large lot of (TO-92 package) 2n5457 transistors, jFET device characteristics are primarily defined by two numerical constants: the Idss current, and the Vgs(off) voltage (often referred to also by its reverse, Vp). These two constants define the family of curves that predicts device behavior in the “active” or “pinch-off” region, a behavioral approximation provided by the following equation:
These two values have a simple visual representation (shown below for an n-channel device, ie., with Vgs(off)<0v), one lying in the Common Source set of transfer curves (right-hand-side with Idss) and the other (left-hand-side with Vgs(off)) lying in the Common Drain set of transfer curves:
(taken from this webpage, edits are mine)
As we see quite often, the left-hand-side of the diagram is oversimplified by showing only one curve, whereas in reality each constant value of Vds yields a curve that is nearly overlapping with the next – hence the reason for often showing only one single curve there. The right-hand-side representation is correctly displayed here.
It should be pointed out at the onset that Vgs(off) and Idss specs vary independently from one another – that is, from one device to another of the same type; this despite an overall average trend. So, for proper characterization either these two constants need to be measured or, at the very least, two separate (wide enough) data points need to be extracted in order to get an orthogonal basis useful in establishing a match across the whole domain (input range) of the characteristics.
Nonetheless, the graph shown above gives a somewhat correct perspective on the location and purpose of these two constants for those who seek to understand what these numbers actually “define”:
Idss, for one, is derived from a key data point that lies on what could be referred to as the “diode curve” within the right-hand-side (Common Source transfer) set of transfer curves. That is, where Vgs = 0 – ie., Gate and Source shorted – as it defines the upper boundary point between the Triode region and the Active (pinch-off) region. Idss also sets the maximum allowable current passing through the device channel, or close enough to the device’s actual true limit.
Vgs(off), next, is defined in the Common Drain transfer curve family, ie., the left-hand-side set of curve(s), and shows the limiting value exactly where drain current becomes zero. This is very useful for determining headroom limits in single-ended gain stages, and control voltage ranges in VCR applications.
It must be stressed that these two values cannot be “measured” exactly, and can only be approximated or inferred indirectly through manual testing. Which brings me to the subject of this post. First, I should say, some approaches are better than others, and some are downright wrong or misleading – betraying a confused or absent understanding of the math involved.
For the sake of doing hobby or home production electronics we would like to combine ease or use with accuracy, or at least reach an acceptable compromise. The following technique shows how to derive a standardized approximation for both values using nothing more than a fresh 9 volt battery and a digital Digital Multi-Meter (DMM) of a certain basic quality. In the later case, we require the input probe impedance of at least 10 Meg ohms; 1 meg is ok, but Zin = 10Meg is much better, and usually available easily and cheaply these days (spec typically provided by DMM manufacturer).
Because, Vgs(off) is defined as the point where Id first becomes zero, there is no way to determine this without some form of interpolation since the transfer curve (very close to being parabolic) is asymptotic to the x-axis. Most approaches, like the one presented here, involves measuring Vgs at a very vey low value of current – as close to zero as reliably possible. By using the very high probe resistance of the DMM to “bias” the D.U.T. jFET to somewhere under 1 uA and yield a voltage measurement at the same time there is no need to include a separate Source resistor like some suggest using.
Idss, can be approximated by diode connecting the D.U.T. jFET (Gate and Source tied together) and measuring the current flowing through the channel when the circuit is closed. Actually, this is one of the commonly used applications for this device, as it will be seen replacing a resistor in certain types of current source designs where the device is then selected specifically for its Idss value – a good example that justifies the need for device characterizing.
Since Idss usually lies somewhere between 1~4mA for most of the devices used in low-voltage audio work, we can leave the circuit connected just long enough to take a reading and thus, a battery won’t get drained (1 second at most). If one is striving for high accuracy and high reliability the user may choose to use a regulated power source instead. But with enough diligence this is not absolutely necessary as a good battery should not take an appreciable hit, even after doing 100 devices (assuming the device is drawing for no more than a split second each time “Idss approx” is measured).
It is important to note that in this scheme we are NOT aiming to measure Idss directly, but instead “a fixed (REFERENCE) operating point” further up on the diode (Vgs=0) curve, one that is still very close to Idss in value. The idea is as follows: trying to measure Idss would require having measured Vgs(off) first and then applying a Drain-Source voltage equal to it, which would bring us to the transition point between Triode Mode and Linear operation zones – exactly where Idss lies. But this would invariably introduce two extra degrees of measurement and adjustment errors, one for measuring Vgs(off), and one for applying it; whereas in this approach we measure the current at a fixed point (@ 9 volt or so, always the same more importantly) along the diode curve.
Since the linear portion of the transfer curves should be relatively flat (ie., low slope) we can use the measured value as a not-so-rough equivalent for Idss. One of the main thing here is that we take this second measurement at the same point all the time so that monotonicity is preserved; ie., one measured values being greater than an other invariably implies that their associated (correct) Idss values are ordered the same.
Hence by letting current pass only long enough to take a measurement reading as to not tire the battery at all ideally (or we use a voltage regulated power source but this adds complexity to the test) we guarantee that this test voltage remains invariable as much as possible – establishing a standardized reference across all DUT’s in the process.
The first and very important goal here is that we end up with two mutually independent data points; and in this case it turns out that our measurement for Idss will be somewhat close to the real value which is also sufficient for the sake of performing secondary ordering. By how much “Idss approx” actually differs from Idss, we can’t say exactly without much analysis – but in principle it should be quite small. For example, in the general SPICE model for jFET devices the Lambda factor is used to indirectly infer the Idss current, whereas Vgs(off) is included directly in the model.
.MODEL 2N5457 NJF(IS=1N VT0=-1.5 BETA=1.125M LAMBDA=2.3M CGD=4PF CGS=5PF)
(see ref: www.wseas.us/e-library/conferences/2007creteee/papers/563-159.pdf)
The only real condition for this scheme to work properly, other than potentially draining the battery (even slightly) is for Vgs(off) to lie somewhat well under the fixed battery voltage. This is true for many of the devices we use in FX design work: J201, 2n5484, 2n5457, etc. The Test Setup schematic above shows the hookup for n-channel devices; for p-channel devices the battery is simply reversed. As well, I have not found jFET’s to be particularly sensitive to temperature – especially through handling (unlike Germanium devices for example). So, in the end, the numbers we obtain this way have a high degree of reliability (assuming the DMM isn’t in error each time).
So, all this means we have a reliable way of at the very least “ordering” our devices within the 2-dimensional range of variation provided by the manufacturer. First, the Vgs(off) estimate that is derived here very likely lies within the error margin of the test setup, providing 2 significant digits (+/- 5m volt). Secondly, even if we are not measuring Idss closely enough for some people’s taste, we can at least use the measured value to order devices (Ron resistance wise) that have identical Vgs(off) measured estimates.
The reason why becomes clear, for example, when the need to match devices in VCR (voltage controlled resistor) applications where a single Cv (control voltage) is used in the circuit implementation of phasor circuits arises. In fact, it is this way in every single jFET phasor ever manufactured; that is, except for my “Paradigm Shifter” where un-matched jFET’s can be used to perform the exact same task in the end).
NOTE: for VCR applications the Idss value plays a secondary “design” role – nonetheless an important one – when grouping devices for their “Ron” (on-resistance) values. That is, once their control range has been established as being the same (ie., applicable to “matched device” designs).
For those who might want to try super matched performance, with every phasor stages shifting identically in range and position, the phasor capacitors can thus be measured and selected to reflect a variation in Idss since what matters is the final RC product in each stage produced by the phasor cap value and the value (normalized to Ron) for each jFET. The final RC products can thus be scaled against the variation in Idss and made near-identical.
In the case where scaled control voltages are used on a set of un-matched jFET’s – ie., with individual Vgs(off) values NOT identical – the same approach can be used to provide near-identical RC products and again produce a peak-performance jFET phasor. See here for a solution to this problem.
Hopefully, this takes some of the mystery out of this whole “jFET matching” thing …
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